Integrated circuit (IC) memory devices store large amounts of data in relatively small physical packages. Typically, an IC memory device comprises a plurality of cells arranged in a matrix of rows and columns. Separate bits of data may be written into, stored, and read out of each of these memory cells.
According to known techniques, redundant (spare) rows and/or columns can be incorporated into IC memory devices to replace defective elements. This allows an otherwise defective memory device to be repaired rather than scrapped, thereby improving the yield and decreasing the cost of manufacture.
In a typical redundancy scheme, if a "normal" element (e.g., row or column) is defective, a comparable redundant element is "enabled" by programming the redundant element to respond to the address of the defective normal element. In addition, the defective element is disabled to prevent it from interfering with the operation of the respective redundant element which replaces it. Both normal elements and redundant elements are selected with corresponding decoders, each of which is responsive to a particular address.
Various techniques have previously been developed to disable defective elements. According to one such technique, a fuse is provided for every normal element or group of normal elements in a memory device. Each fuse can be selectively blown, for example, with a properly aimed burst of light from a LASER, in order to disable the respective element or group of elements. This technique of using fuses is problematic in that fuses generally require large amounts of surface area to implement. Furthermore, each fuse must be on the pitch (row to row spacing) of the memory cells which are supported. While the rows on a modern memory device (e.g., a modern dynamic random access memory (DRAM)) are on a pitch of less than one-half micron, fuses are on a minimum pitch of many microns. To compensate for this difference in pitch between rows and fuses, many rows may be grouped, and accordingly, disabled, together. Thus, when a single row is defective, it along with perhaps seven other rows are all replaced, even if the seven other rows are not defective. This is very inefficient, requires large amounts of additional chip area, and increases the cost of manufacture.
Another technique uses logic circuitry to de-select a defective normal element when a redundant element is selected as a replacement. In this technique, whenever any redundant element is selected (i.e., its programmed address is present at the corresponding redundant decoder), a buffered output from the selected redundant decoder drives an extra input on each of a large number of normal decoders to disable these normal decoders. During operation, upon receipt of the address of the defective element, the normal decoder for the defective normal element initially responds to its corresponding address and then shuts off when it subsequently receives the buffered redundant select signal indicating that the redundant element has also been selected. This creates extra delay between the time that the normal and redundant decoders are first selected and the time that the normal decoder is logically deselected. Such delay can be as high as ten percent (10%) of the total access time for a memory device. Thus, this technique for disabling a defective element adversely affects the performance of the memory device.
Yet another technique for disabling a defective normal element requires two separate decoders--a main decoder and a direct current (DC) decoder--for each normal element. For a particular normal element, the main decoder receives and conditionally responds to the address input to the chip. After programming a redundant element, its DC address bus always contains the address of the defective element. The respective DC decoder then permanently disables its normal decoder. To accomplish this, a separate DC address bus must be provided for each redundant element. Also, separate DC decoders must be provided for each normal element for each DC address bus. The buses for the DC decoders and DC decoders themselves, however, can consume significant chip area, especially when numerous redundant elements are provided. Such use of area increases the cost of each chip.